`timescale 1ns/1ps
module TXD_test;
reg clk;
reg rst;
reg [7:0] datain;
reg wrsig;
wire tx;
wire idle;
wire send;
wire wrsigbuf,wrsigrise;
wire presult;			//奇偶校验位
reg [7:0] cnt;

always #5 clk=~clk;     //16?????
initial begin
    clk=0;rst=0;
  #10 rst=1;datain=8'b1111_1101;wrsig=1'b1;
  #3000 $stop;
end

initial $monitor($time, , ,"clk=%d rst=%d idle=%d wrsig=%d cnt=%d tx=%d send=%d presult=%d",clk,rst,idle,wrsig,cnt,tx,send,presult); 

endmodule
